1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device and a writing method therefor, and more particularly to a nonvolatile semiconductor memory device capable of electrically rewriting information and a writing method therefor.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a portion of a memory cell array of a conventional nonvolatile semiconductor memory device (EEPROM) disclosed in "A 128K Flash EEPROM using Double Polysilicon Technology", ISSCC Digest of Technical Papers, pp. 76-77, 1987. In FIG. 1, voltages for writing and erasing each of the memory transistors are also disclosed.
Referring to the figure, memory transistors Q1 to Q4 are MOS transistors each provided with a floating gate, and each forming one memory cell. The memory transistors are arranged in a matrix and the respective source electrodes thereof connected with a source line SL common to all the cells. A bit line connects the drain electrodes of the memory transistors in the same column (in FIG. 1, two bit lines BL1 and BL2 are shown). A word line connects the control gates of the memory transistors in the same row (in FIG. 1, two word lines WL1 and WL2 are shown). Although FIG. 1 shows four memory transistors as representatives, a memory cell array usually comprises a larger number of memory transistors.
FIG. 2 shows a cross-sectional structure of the memory transistors Q1 to Q4 shown in FIG. 1. Referring to FIG. 2, a drain diffused region 2 and a source diffused region 3 are formed spaced apart from each other by a prescribed distance on a surface of a semiconductor substrate 1. The semiconductor substrate 1 is covered with a thin oxide film 4 of about 200 .ANG. in thickness. A floating gate 5 is provided on the oxide film such that a portion of the floating gate 5 is opposed to an end portion of the drain diffused region 2. The floating gate 5 and the oxide film 4 are covered with an oxide film 6 and the oxide 6 is further covered by a control gate 7. Therefore, the control gate has a low step at the portion where the floating gate 5 does not exist. The floating gate 5 is in an electrically floating state surrounded by the oxide films 4 and 6. A drain electrode 8, a control gate electrode 9 and a source electrode 10 are respectively connected to the drain diffused region 2, the control gate 7 and the source diffused region 3.
The writing operation of the above described conventional device will be described in the following.
First, an erasing cycle is carried out in which "1" is written in all the memory transistors. The erasing cycle is completed by applying a high voltage V.sub.PP to all the bit lines (BL1 and BL2 in FIG. 1) and by applying "L" level (0 V) to all the word lines (WL.sub.1 and WL.sub.2 in FIG. 1). By doing so, a high electric field is generated between the floating gate 5 and the drain diffused region 2 of all the memory transistors (Q1 to Q4 in FIG. 1). Therefore, electrons stored in the floating gate 5 are drawn into the drain diffused region 2 through the thin oxide film 4 by electron tunneling. Consequently, the floating gate 5 is depleted of electrons and accordingly a threshold voltage of each of the memory transistors Q1 to Q4 viewed from the control gate 7 is lowered (becomes negative level). A logic "1" is assigned to that state.
When the erasing cycle is finished, a writing cycle begins. The writing cycle is carried out in the similar manner as the program opertion in an EPROM. More specifically, a high voltage V.sub.PP is applied to a selected bit line (BL.sub.2 in FIG. 1) while 0 V is applied to the non-selected bit line (BL.sub.1 in FIG. 1). A high voltage V.sub.PP is applied to the selected word line (WL.sub.1 in FIG. 1) while 0 V is applied to the non-selected word line (WL.sub.2 in FIG. 1). Consequently, a high voltage V.sub.PP is applied to the drain diffused region 2 and to the control gate 7 of the selected memory transistor (Q3 in FIG. 1). At this time, hot electrons are generated in the vicinity of the drain diffused region 2 of the selected memory transistor Q3, and the hot electrons are accelerated by the high voltage V.sub.PP applied to the control gate 7 so as to be introduced into the floating gate 5. As a result, electrons are stored in the floating gate 5, and a threshold voltage of the memory transistor Q3 viewed from the control gate 7 becomes higher (becomes positive level). Thus, a logic "0" is written in the selected memory cell. Meanwhile, the source line SL is always set at "L" level.
In the above described EEPROM having 1 transistor.1 memory cell structure, it is not necessary to erase stored information using ultraviolet rays as required in an EPROM and the information can be electrically erased, thereby enabling simple rewriting operation. In addition, one memory cell can be formed by a single transistor, not by two transistors as in an EEPROM, and thus, chip area can be reduced.
A conventional EEPROM having 1 transistor.1 memory cell structure is structured as described above, and writing of the logic "0" into the selected memory transistor is carried out by introducing hot electrons. However, if the high voltage V.sub.PP is obtained by internally boosting an output voltage V.sub.CC from the external power supply, the current driving capacity is small, so that sufficient hot electrons can not be introduced. Therefore, there was a disadvantage that a power supply capable of generating a high voltage V.sub.PP is required as an external power supply, and a single power supply having V.sub.CC level is not sufficient for carrying out the operation.
In addition, if the writing is done by introducing hot electrons, a number of excessive electrons are generated in the thin oxide film 4, causing degradation of the said oxide film 4. Therefore, there was a disadvantage that the number of reliable rewriting is relatively small (about 1000 times).
Furthermore, since the writing is carried out in the memory transistors one by one, several milliseconds are required for writing 1 byte, so that the writing of the whole chip takes a long period of time.